A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 µm CMOS

Document Type : Researsh Articles

Authors

• mohsen dashtbayazi ¹
• Mohammad Taherzadeh Sani ²
• Samaneh Babayan Mashhadi ³
• Ehsan Rahiminejad ²

¹ Faculty of Engineering, Ferdowsi University of Mashhad

² Faculty of Engineering, Ferdowsi University

³ Imam Reza University

10.22067/ess.v2i2.35705

Abstract

In this paper, a low power SAR Analog to Digital Converter (ADC) with a resolution of 10 bits and a sampling rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous process with an optimized D/A timing strategy to increase its sampling frequency. This ADC is simulated in a 130-nm CMOS technology with two power supplies of 0.6 V and
1.2 V. It achieves an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM = 5.3 to 9.3 fJ/conv.-step.

Keywords

• Analog to Digital Converter
• asynchronous process
• power efficiency
• asynchronous clock generator circuit
• low power designs

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